At Weasic we’re committed to address the industry’s toughest challenges in mmWave design applications. We are the best team, that is why the best companies in the world choose to partner with us. Working at Weasic goes beyond the stereotypical start-up workplace. We are offering an environment where knowledge sharing, personal and professional advancement is encouraged.

 

If you’re interested to join our team please send your resume at: jobs@weasic.com

Location: Maroussi, Greece

 

General Overview:

The Office Manager will report to the company CEO. Will be an assistant to the CEO, responsible to organize the company’s daily operations, overview processes, maintain schedules, deadlines and ensure timely implementation of various operational tasks.

 

Responsibilities:

  • Perform a broad range of administrative and secretarial tasks
  • Overview and ensure implementation of various corporate processes, including HR related
  • Manage and organize company’s daily operations and functions
  • Communicate with suppliers, partners and customers. Assist in scheduling meetings, online sessions, etc.
  • Organize company’s participation to exhibitions and tradeshows

 

Qualifications and Requirements:

  • Bachelor’s in Business Administration or equivalent Academic degree
  • 10+ years of experience in a similar position
  • Past experience in an HR dept a definite plus
  • Excellent command of the English and Greek language in both oral and written form
  • Advanced level of experience in MS Word and Excel

 

Personal attributes:

  • Ability to work with a sense of urgency and thrive in a dynamic environment
  • Exceptional organizational and communication skills
  • Consistent, diligent, committed to meeting deadlines and delivering high-quality work
  • Discrete, professional and pleasant demeanor

 

In addition to competitive salaries and fringe benefits, our associates enjoy a casual, team-oriented work environment. Candidates are requested to send their CVs only at jobs@weasic.com with subject “Application for Office Manager Position”.

Location: Athens, Greece

 

General Overview:

  • Senior Analog Design Engineer with expertise on high-performance analog circuits. Responsible for specification, architecture, design and development of analog integrated circuits from initial concept through production ramp up. The successful candidate in this role will do high-performance, transistor-level design, starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

 

Responsibilities:

  • Develop and implement CMOS/SOI/BiCMOS analog circuitry such as high precision voltage references, LDOs, filters, OPAMPs, OTAs
  • Responsible for specification, architecture, design and development of analog integrated circuits from initial concept through production ramp up
  • Define circuit requirements and complete design, from schematic, layout, and verification to characterization
  • Optimize circuits to meet specifications for system performance
  • Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings
  • Perform pre and post layout verification checks like EMIR and ageing simulations and optimization
  • Provide support for post-silicon bring-up and debugging

 

Qualifications and Requirements:

  • Bachelor’s degree in Electrical Engineering or equivalent degree and 10+ years’ experience, or Master’s degree in the same and 8+ years’ experience, or PhD degree in the same and 5+ years’ experience or equivalent education and experience
  • 5+ years of experience in high-performance Analog IC development in advanced CMOS/BiCMOS processes
  • Must have a track record of successfully taking designs to production
  • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
  • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis
  • Deep understanding of analog design concepts such as analysis of stability, linearity, noise and mismatch
  • Experience with design, verification and layout parasitic extraction tools (Cadence’s IC design environment, PVS, QRC, Calibre)
  • Familiarity with packaging effects, supply related issues, ESD structures and substrate coupling effects

 

Personal attributes:

  • Self-starter with the ability to assume leadership roles and adhere to schedules
  • Ability to work with a sense of urgency and thrive in a dynamic environment
  • Exceptional interpersonal and communication skills, critical for working, influencing and collaborating with other Weasic design teams
  • Consistent, professional, diligent, committed to meeting deadlines and delivering high-quality, state-of-the-art designs
  • Must be able to seek help proactively as well as share and pass on knowledge

Location: Athens, Greece

 

General Overview:

  • Senior Analog/Mixed-Signal Design Engineer with expertise on high-performance analog-to-digital and digital-to-analog converters. Responsible for the design of analog and mixed-signal blocks inside the radio or as stand-alone products, starting from concept and transistor-level feasibility studies. Will oversee layouts and verify designs to ensure a successful tape-outs. The successful candidate in this role will do high-performance, transistor-level design, starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

 

Responsibilities:

  • Develop and implement analog and mixed-signal circuits with emphasis on converters
  • Define circuit requirements and complete design, from schematic, layout, and verification to characterization
  • Optimize circuits to meet specifications for system performance
  • Work closely with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings
  • Perform pre and post layout verification checks like EMIR and ageing
  • Provide support for post-silicon bring-up and debugging

 

Qualifications and Requirements:

  • Bachelor’s degree in Electrical Engineering or equivalent degree and 10+ years’ experience, or Master’s degree in the same and 8+ years’ experience, or PhD degree in the same and 5+ years’ experience or equivalent education and experience
  • Expert in high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques.
  • 5+ years of experience in high-performance Analog/Mixed-Signal IC development in advanced CMOS/SOI and/or SiGe processes
  • Experience with high-speed interfaces will be considered a plus
  • Must have a track record of successfully taking designs to production
  • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
  • Good knowledge of calibration and production testing techniques
  • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis
  • Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments
  • Experience with design, verification and layout parasitic extraction tools (Cadence’s IC design environment, PVS, QRC, Calibre, circuit simulation tools like Spectre, HSpice, or other similar tools)
  • Familiarity with packaging effects, supply related issues, ESD structures, and substrate coupling effects

 

Personal attributes:

  • Self-starter with the ability to assume leadership roles and adhere to schedules
  • Ability to work with a sense of urgency and thrive in a dynamic environment
  • Exceptional interpersonal and communication skills, critical for working, influencing and collaborating with other Weasic design teams
  • Consistent, professional, diligent, committed to meeting deadlines and delivering high-quality, state-of-the-art designs
  • Must be able to seek help proactively as well as share and pass on knowledge

Location: Athens, Greece

General Overview:

  • Responsible for the development and implementation of digital and mixed-signal SoC circuits. Has a leading role in design architecture, specifications, layout guidance, production testing, characterization and qualification. Responsible for delivering the digital IP block and integrating it into the SOC.

 

Responsibilities:

  • Develop and own physical design implementation of multi-hierarchy, low-power designs including physical-aware logic synthesis, design for testability, static timing analysis, formal verification, gate-level functional & timing ECO in advanced technology nodes
  • Develop & document STA & Synthesis strategies
  • Verify SOCs using SystemVerilog, testbenches, checkers, models and tests. Work with Analog/RF design team to achieve system-level, mixed-mode verification goals
  • Define, document, develop and execute RTL verification test/coverage at system level
  • Block and Chip-level floor planning, analysis of floor plan options taking into account timing and area budgets
  • Place and route, timing closure and power analysis
  • Responsible for System-Level and Digital Backend design closure including floor planning, synthesis, DFT, port locations, timing closure, and IP design rules

 

Qualifications and Requirements:

  • Master’s or PhD in Electrical Engineering and 7+ years of experience in digital system design
  • Deep understanding of the digital design flow from architecture, RTL design and simulation – logic synthesis and timing constraints – post synthesis/post layout gate level simulation
  • Strong design and system knowledge
  • Excellent knowledge of Verilog and VHDL hardware description languages
  • Knowledge of all digital verification steps (RTL, gate level, formal verification)
  • Experience in chip/block level floor planning and P&R
  • Strong experience in timing analysis and timing closure, taking responsibility for increasingly complex designs
  • Strong experience in modern digital ASIC methodologies including front-end RTL design, synthesis, DfT and physical implementation
  • Experience using advanced node rules, including power and testability support/optimization
  • Experience in crosstalk noise analysis, physical verification, LVS and DRC
  • Experience in DFT, MBIST, scan, coverage
  • Experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis)
  • Experience with Cadence EDA tools spanning the RTL to GDSII, considered a plus
  • Scripting skills in Perl/Python/TCL would be desirable
  • Experience in documentation creation and implementation
  • Experience with Automotive is a strong plus

 

Personal attributes:

  • Self-starter with the ability to assume leadership roles
  • Ability to work with a sense of urgency and thrive in a dynamic environment
  • Exceptional interpersonal and communication skills, critical for working, influencing and collaborating with other Weasic design teams
  • Consistent, professional, diligent, committed to meeting deadlines and delivering high-quality, state-of-the-art designs
  • Ability to contribute to a multi-disciplinary team in a constructive and data-driven approach

Μain responsibilities:

  • Analog and mixed signal transceiver sub-blocks layout and design.

Minimum education/qualifications requirements:

  • Bachelor’s degree in Electrical Engineering, Physics or related field
  • Basic knowledge of analog/digital circuit design and MOS device physics
  • Programming skills in Matlab, Python or scripting languages
  • Experience with Cadence layout design and verification tools will be considered as a plus
  • Fluency in English language
  • Valid Greek work permit