At Weasic we’re committed to address the industry’s toughest challenges in mmWave design applications. We are the best team, that is why the best companies in the world choose to partner with us. Working at Weasic goes beyond the stereotypical start-up workplace. We are offering an environment where knowledge sharing, personal and professional advancement is encouraged.


If you’re interested to join our team please send your resume at:

Location: Athens, Greece

General Overview:

  • Responsible for the development and implementation of digital and mixed-signal SoC circuits. Has a leading role in design architecture, specifications, layout guidance, production testing, characterization and qualification. Responsible for delivering the digital IP block and integrating it into the SOC.



  • Develop and own physical design implementation of multi-hierarchy, low-power designs including physical-aware logic synthesis, design for testability, static timing analysis, formal verification, gate-level functional & timing ECO in advanced technology nodes
  • Develop & document STA & Synthesis strategies
  • Verify SOCs using SystemVerilog, testbenches, checkers, models and tests. Work with Analog/RF design team to achieve system-level, mixed-mode verification goals
  • Define, document, develop and execute RTL verification test/coverage at system level
  • Block and Chip-level floor planning, analysis of floor plan options taking into account timing and area budgets
  • Place and route, timing closure and power analysis
  • Responsible for System-Level and Digital Backend design closure including floor planning, synthesis, DFT, port locations, timing closure, and IP design rules


Qualifications and Requirements:

  • Master’s or PhD in Electrical Engineering and 7+ years of experience in digital system design
  • Deep understanding of the digital design flow from architecture, RTL design and simulation – logic synthesis and timing constraints – post synthesis/post layout gate level simulation
  • Strong design and system knowledge
  • Excellent knowledge of Verilog and VHDL hardware description languages
  • Knowledge of all digital verification steps (RTL, gate level, formal verification)
  • Experience in chip/block level floor planning and P&R
  • Strong experience in timing analysis and timing closure, taking responsibility for increasingly complex designs
  • Strong experience in modern digital ASIC methodologies including front-end RTL design, synthesis, DfT and physical implementation
  • Experience using advanced node rules, including power and testability support/optimization
  • Experience in crosstalk noise analysis, physical verification, LVS and DRC
  • Experience in DFT, MBIST, scan, coverage
  • Experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis)
  • Experience with Cadence EDA tools spanning the RTL to GDSII, considered a plus
  • Scripting skills in Perl/Python/TCL would be desirable
  • Experience in documentation creation and implementation
  • Experience with Automotive is a strong plus


Personal attributes:

  • Self-starter with the ability to assume leadership roles
  • Ability to work with a sense of urgency and thrive in a dynamic environment
  • Exceptional interpersonal and communication skills, critical for working, influencing and collaborating with other Weasic design teams
  • Consistent, professional, diligent, committed to meeting deadlines and delivering high-quality, state-of-the-art designs
  • Ability to contribute to a multi-disciplinary team in a constructive and data-driven approach

Main responsibilities:

  • Design of complex circuits such as LVDS drivers, High speed interfaces, all-digital PLLs, Analog to Digital converters

Minimum education/qualifications requirements:

  • Master’s or PhD, Electrical Engineering and/or Computer Engineering
  • 5+ years of experience in analog and/or mixed-signal design in deep sub-micron CMOS processes
  • Analog / mixed-signal behavioural modeling skills
  • Valid Greek work permit

Μain responsibilities:

  • Analog and mixed signal transceiver sub-blocks layout and design.

Minimum education/qualifications requirements:

  • Bachelor’s degree in Electrical Engineering, Physics or related field
  • Basic knowledge of analog/digital circuit design and MOS device physics
  • Programming skills in Matlab, Python or scripting languages
  • Experience with Cadence layout design and verification tools will be considered as a plus
  • Fluency in English language
  • Valid Greek work permit